The present invention relates to a field effect semiconductor device and a manufacturing method thereof. More particularly the present invention relates to a semiconductor device composed of field effect transistors for integrated circuits and a manufacturing method thereof suited to higher performance and higher reliability.
In the field of field effect devices using silicon semiconductors and including, for example, integrated circuits employing MOS transistors, the size of the constituent elements is becoming smaller and smaller. Thus, research and development is conducted in the region of submicrons. The structure and manufacturing method have improved but, for miniature elements (i.e. MOS) due to miniaturization, worsening of reliability due to effects such as short channel effect and hot carrier effect is observed. Thus, such a device must be operated with a reduced supply voltage.
Due to this situation, studies of devices with novel structure are being promoted. For example, a structure and manufacturing method relating to GOLD (gate-drain overlapped lightly doped drain) technology has been found to allow for an increased supply voltage to be fed to the MOS transistor (Izawa et al., International Electron Device Meeting Technical Digest of Papers, pp. 38-41, 1987, which is hereby incorporated by reference for its teaching on GOLD technology). To help understand the background of the conventional MOS technology, the manufacturing method relating to GOLD Technology is explained below. FIG. 9(a) to (d) are process sectional views for explaining the manufacturing method of a MOS transistor which is based upon GOLD.
As shown in FIG. 9(a), a gate oxide film 112, a thin lower layer polysilicon film 120, thick upper layer polysilicon layer 150 and a silicon oxide layer 160 are sequentially formed on a p-type monocrystalline silicon semiconductor layer 100 to compose a multilayer film. On the gate forming area thereof, a resist pattern 170 is formed by ordinary photolithographic process. Between the thin polysilicon 120 and the thick polysilicon 150, a natural residual oxide film with a thickness of 0.5 to 1 nanometer is formed.
As shown in FIG. 9(b), after forming an oxide film pattern 160A by masking the resist pattern, and by further using this oxide pattern 160A as a mask, the thick upper layer polysilicon 150 is etched to the oxide film using a dry etching technique having a high selective ratio. At this time, the natural oxide film on the surface of the thin lower layer polysilicon 120 is used to inhibit further etching, and the polysilicon 150 is etched in an isotropic shape, thereby forming a polysilicon pattern 150A. By, using the oxide film pattern 160A and polysilicon pattern 150A as the mask, phosphorus ions are implanted to form n-type semiconductor regions 200A, 200B which are formed as a source and a drain in the p-type semiconductor layer 100.
As shown in FIG. 9(c), on the side surfaces of oxide film pattern 160A and polysilicon pattern 150A, silicon oxide films 210A, 210B are selectively left over by anisotropic etching. By using oxide films 210A, 210B as a mask, the thin silicon film is etched and a polysilicon pattern 120A is formed substantially as a gate electrode.
Finally, as shown in FIG. 9(d), using the remaining oxide films 210A and 210B as the mask, arsenic ions of high concentration are implanted to form n-type semiconductor regions 220A, 220B as part of the source and part of the drain in the p-type semiconductor layer 100.
Structural features of thus fabricated GOLD components include the following. The n-type semiconductor region 200B at the end part of the drain sufficiently overlaps (by more than 0.2 microns the polysilicon pattern 120A for the gate electrode). By virtue of this overlap, the electric field which is applied to the drain end is smaller as compared with the MOS element formed in an ordinary method (for example, MOS or LDD [lightly doped drain] structure), generation of a hot carrier in the drain end part of GOLD is suppressed, and a device of excellent reliability (life time) is obtained. In addition, the so-called short channel effect, with its threshold voltage (Vt) which declines as the channel length decreases is small as compared with the conventional MOS. Thus, a MOS device which is small in effective channel length is realized. Since the channel length can be shortened, the mutual conductance is large, and a MOS transistor with a powerful driving ability is obtained.
However, in the conventional etching process of gate electrodes shown in FIG. 9(b), the following problems are known:
(1) Since an extremely thin natural oxide film is used to inhibit etching, a special etchant for dry etching with a large etching selective ratio (more than several hundred times) is required to etch the thick upper layer polysilicon 150.
(2) At the present, a polysilicon etchant (as used in isotropic etching) is capable of etching several hundred times faster than the oxide film. This results in pattern thinning in the upper polysilicon 150. As a result, the wiring resistance of the upper polysilicon wiring increases. As the wiring resistance increases, high speed signal input response to the gate decreases.
(3) As pattern thinning of the upper polysilicon 150 occurs, the oxide film pattern 160A becomes overhung, and coverage of oxide films 210A and 210B left over on the side surface of polysilicon pattern 150A decreases. Since this oxide film is used at the etching mask of the lower polysilicon as the gate electrode, it often leads to fluctuations of gate wiring width (gate length).
(4) When a thick oxide film of over 3 nanometers is used instead of the thin natural oxide film of about 1 nanometer, the electrical connection between the upper layer polysilicon 150 and the lower layer polysilicon 120 becomes poor.
(5) The gate length of the polysilicon gate electrode 120A shown in FIG. 9(c), (d) is greater than the length of the silicon oxide film 160A which is usually processed in the minimum dimension) by the thickness of the left-over silicon oxide films 210A, 210B (called side walls). Hence the gate length of the polysilicon gate electrode 120A is greater than the gate length of a conventional MOS, thus resulting in poor integration.
It is, hence, a primary object of the invention to present a novel gate-drain overlap structure and its manufacturing method in order to solve the forming problems of the gate electrodes of such gate-drain overlap MOS structures of the prior art.